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Features
TC4467/TC4468/TC4469
General Description
The TC4467/TC4468/TC4469 devices are a family of four-output CMOS buffers/MOSFET drivers with 1.2 A peak drive capability. Unlike other MOSFET drivers, these devices have two inputs for each output. The inputs are configured as logic gates: NAND (TC4467), AND (TC4468) and AND/INV (TC4469). The TC4467/TC4468/TC4469 drivers can continuously source up to 250 mA into ground referenced loads. These devices are ideal for direct driving low current motors or driving MOSFETs in a H-bridge configuration for higher current motor drive (see Section 5.0 for details). Having the logic gates onboard the driver can help to reduce component count in many designs. The TC4467/TC4468/TC4469 devices are very robust and highly latch-up resistant. They can tolerate up to 5 V of noise spiking on the ground line and can handle up to 0.5 A of reverse current on the driver outputs. The TC4467/4468/4469 devices are available in commercial, industrial and military temperature ranges.
Logic-Input CMOS Quad Drivers
* High Peak Output Current: 1.2 A * Wide Operating Range: - 4.5 V to 18 V * Symmetrical Rise/Fall Times: 25 nsec * Short, Equal Delay Times: 75 nsec * Latch-proof. Will Withstand 500 mA Inductive Kickback * 3 Input Logic Choices: - AND / NAND / AND + Inv * ESD Protection on All Pins: 2 kV
Applications
* * * * * * General Purpose CMOS Logic Buffer Driving All Four MOSFETs in an H-Bridge Direct Small Motor Driver Relay or Peripheral Drivers CCD Driver Pin-Switching Network Driver
Package Types
14-Pin PDIP/CERDIP
1A 1 1B 2 2A 3 2B 4 3A 5 3B 6 GND 7 TC4467 TC4468 TC4469 14 VDD 13 1Y 12 2Y 11 3Y 10 4Y 9 4B 8 4A
16-Pin SOIC (Wide)
1A 1B 2A 2B 3A 3B GND GND 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VDD VDD 1Y 2Y 3Y 4Y 4B 4A
TC4467 TC4468 TC4469
2002 Microchip Technology Inc.
DS21425B-page 1
TC4467/TC4468/TC4469
Logic Diagrams
TC4467
VDD 14 1A 1B 2A 2B 3A 3B 4A 4B
1 2 3 4 5 6 8 9
TC4468
VDD 14 13 1Y 1A 1 1B 2 2A 3 2B 4 3A 5 3B 6 4A 8 4B 9 7 GND 13 1Y 12 2Y 11 10 3Y 4Y 1A 1 1B 2 2A 3 2B 4 3A 5 3B 6 4A 8 4B 9
TC4469
VDD 14 13 1Y 12 2Y 11 10 7 GND 3Y 4Y
TC446X
VDD
12 2Y 11 3Y 10 4Y 7 GND
Output
DS21425B-page 2
2002 Microchip Technology Inc.
TC4467/TC4468/TC4469
1.0 ELECTRICAL CHARACTERISTICS
Notice: Stresses above those listed under "Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.
Absolute Maximum Ratings
Supply Voltage ...............................................................+20 V Input Voltage ............................. (GND - 5 V) to (VDD + 0.3 V) Package Power Dissipation: (TA 70C) PDIP...................................................................800 mW CERDIP .............................................................840 mW SOIC ..................................................................760 mW Package Thermal Resistance: CERDIP R J-A ...................................................100C/W CERDIP R J-C .....................................................23C/W PDIP R J-A ..........................................................80C/W PDIP R J-C ..........................................................35C/W SOIC RJ-A ..........................................................95C/W SOIC RJ-C ..........................................................28C/W Operating Temperature Range: C Version ................................................... 0C to +70C E Version.................................................-40C to +85C M Version ..............................................-55C to +125C Maximum Chip Temperature ....................................... +150C Storage Temperature Range.........................-65C to +150C
ELECTRICAL SPECIFICATIONS
Electrical Characteristics: Unless otherwise noted, TA = +25C, with 4.5 V VDD 18 V. Parameters Input Logic 1, High Input Voltage Logic 0, Low Input Voltage Input Current Output High Output Voltage Low Output Voltage Output Resistance Peak Output Current Continuous Output Current Latch-Up Protection Withstand Reverse Current Switching Time (Note 1) Rise Time Fall Time Delay Time Delay Time Power Supply Power Supply Current Power Supply Voltage
Note 1: 2: 3:
Sym VIH V IL IIN VOH VOL RO IPK IDC I
Min 2.4 -- -1.0 VDD - 0.025 -- -- -- -- -- --
Typ -- -- -- -- -- 10 1.2 -- -- 500
Max VDD 0.8 +1.0 -- 0.15 15 -- 300 500 --
Units V V A V V A mA mA Single Output Note 3 Note 3
Conditions
0 V VIN VDD ILOAD = 100 A (Note 1) ILOAD = 10 mA (Note 1) IOUT = 10 mA, VDD = 18 V
Total Package 4.5 V VDD 16 V
tR tF tD1 tD2 IS VDD
-- -- -- -- -- 4.5
15 15 40 40 1.5 --
25 25 75 75 4 18
nsec nsec nsec nsec mA V
Figure 4-1 Figure 4-1 Figure 4-1 Figure 4-1
Note 2
Totem pole outputs should not be paralleled because the propagation delay differences from one to the other could cause one driver to drive high a few nanoseconds before another. The resulting current spike, although short, may decrease the life of the device. Switching times are ensured by design. When driving all four outputs simultaneously in the same direction, VDD will be limited to 16 V. This reduces the chance that internal dv/dt will cause high-power dissipation in the device. The input threshold has approximately 50 mV of hysteresis centered at approximately 1.5 V. Input rise times should be kept below 5 sec to avoid high internal peak currents during input transitions. Static input levels should also be maintained above the maximum, or below the minimum, input levels specified in the "Electrical Characteristics" to avoid increased power dissipation in the device.
2002 Microchip Technology Inc.
DS21425B-page 3
TC4467/TC4468/TC4469
ELECTRICAL SPECIFICATIONS (OPERATING TEMPERATURES)
Electrical Characteristics: Unless otherwise noted, over operating temperature range with 4.5 V VDD 18 V. Parameters Input Logic 1, High Input Voltage Logic 0, Low Input Voltage Input Current Output High Output Voltage Low Output Voltage Output Resistance Peak Output Current Continuous Output Current Latch-Up Protection Withstand Reverse Current Switching Time (Note 1) Rise Time Fall Time Delay Time Delay Time Power Supply Power Supply Current Power Supply Voltage
Note 1: 2: 3:
Sym VIH V IL IIN VOH VOL RO IPK IDC I
Min 2.4 -- -10 VDD - 0.025 -- -- -- -- -- --
Typ -- -- -- -- -- 20 1.2 -- -- 500
Max -- 0.8 10 -- 0.30 30 -- 300 500 --
Units V V A V V A mA mA Single Output Note 3 Note 3
Conditions
0 V VIN VDD ILOAD = 100 A (Note 1) ILOAD = 10 mA (Note 1) IOUT = 10 mA, VDD = 18 V
Total Package 4.5 V VDD 16 V
tR tF tD1 tD2 IS VDD
-- -- -- -- -- 4.5
15 15 40 40 -- --
50 50 100 100 8 18
nsec nsec nsec nsec mA V
Figure 4-1 Figure 4-1 Figure 4-1 Figure 4-1
Note 2
Totem pole outputs should not be paralleled because the propagation delay differences from one to the other could cause one driver to drive high a few nanoseconds before another. The resulting current spike, although short, may decrease the life of the device. Switching times are ensured by design. When driving all four outputs simultaneously in the same direction, VDD will be limited to 16 V. This reduces the chance that internal dv/dt will cause high-power dissipation in the device. The input threshold has approximately 50 mV of hysteresis centered at approximately 1.5 V. Input rise times should be kept below 5 sec to avoid high internal peak currents during input transitions. Static input levels should also be maintained above the maximum, or below the minimum, input levels specified in the "Electrical Characteristics" to avoid increased power dissipation in the device.
TRUTH TABLE
Part No. Inputs A Inputs B Outputs TC446X Legend: H = High H H L L = Low TC4467 NAND H L H L H H L L H H H H TC4468 AND H L L L H L L L L H H L TC4469 AND/INV H L H L H L L L L
DS21425B-page 4
2002 Microchip Technology Inc.
TC4467/TC4468/TC4469
2.0
Note:
TYPICAL PERFORMANCE CURVES
The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. TA = +25C, with 4.5 V VDD 18 V.
Note:
140
2200 p 0 pF
140 120 2200 pF 100
tFALL (nsec)
1500 pF
120 100
tRISE (nsec)
1600 p pF 1000 pF
80 60 40 20 0 3
80 60 40 20
1000 pF
470 pF
470 pF 100 pF
100 p pF
5
7
9
11 13 VSUPPLY (V)
15
17
19
0
3
5
7
9
11 13 VSUPPLY (V)
15
17
19
FIGURE 2-1: Voltage.
Rise Time vs. Supply
FIGURE 2-4: Voltage.
140
Fall Time vs. Supply
140 120 100
tRISE (nsec)
5V
120 100
tFALL (nsec)
5V
80 60 40 20 0 100 1000 CLOAD (pF)
10,000
80 60 40 20 0 100 1000 CLOAD (pF)
10 V 15 V
10 V 15 V
10,000
FIGURE 2-2: Load.
25 20 TIME (nsec) 15 10 5 0 -50
VSUPPLY = 17.5 V CLOAD = 470 pF
Rise Time vs. Capacitive
FIGURE 2-5: Load.
80
Fall Time vs. Capacitive
CLOAD = 470 pF 4
tFALL tRISE
DELAY TIME (nsec)
60
tD1
40
tD2
20
0
-25
0
25
50
75
100
125
4
6
8
10
12
14
16
18
TEMPERATURE (C)
VSUPPLY (V)
FIGURE 2-3: Temperature.
Rise/Fall Times vs.
FIGURE 2-6: Supply Voltage.
Propagation Delay Time vs.
2002 Microchip Technology Inc.
DS21425B-page 5
TC4467/TC4468/TC4469
2.0
Note:
TYPICAL PERFORMANCE CURVES (CONTINUED)
TA = +25C, with 4.5 V VDD 18 V.
140
VDD = 12 V
70 INPUT RISING DELAY TIME (nsec) 60 50
tD2 VDD = 17.5 V = 470 pF VIN
120 DELAY TIME (nsec) 100 80 60 40 20 0 1 2 3 4 5 6 VDRIVE (V) 7 8 9
10
tD1
tD2
INPUT FALLING
tD1
40 30 20 -60
-40
-20
0
20
40
60 C)
80
100
120
FIGURE 2-7: Times.
2.5
Input Amplitude vs. Delay
FIGURE 2-10: vs. Temperatures.
3.5
VDD = 17.5 V
Propagation Delay Times
3.0
IQUIESCENT (mA) IQUIESCENT (mA)
2.0 1.5 1.0 0.5 0 4 6 8 10 12 VSUPPLY (V) 14 16 18 OUTPUTS = 1 OUTPUTS = 0
2.5 2.0 1.5 1.0 0.5 0 -60 -40 -20 0 20 40 60 TJUNCTION (C) 80 100
120
OUTPUTS = 0
OUTPUTS = 1
FIGURE 2-8: Quiescent Supply Current vs. Supply Voltage.
35 30 25
FIGURE 2-11: vs. Temperature.
35 30
Quiescent Supply Current
RDS(ON) ()
TJ = +150C
25
20 15 10 5 0 4 6 8 10 12 V SUPPLY (V) 14 16 18
TJ = +25C
RDS(ON) ()
20
TJ = +150C
15 10 5 0 4 6 8
TJ = +25C
10 12 V (V) SUPPLY
14
16
18
FIGURE 2-9: Resistance.
High-State Output
FIGURE 2-12: Resistance.
Low-State Output
DS21425B-page 6
2002 Microchip Technology Inc.
TC4467/TC4468/TC4469
2.0
Note:
TYPICAL PERFORMANCE CURVES (CONTINUED)
(Load on single output only).
60
VDD = 18 V
2 MHz H 1 MHz MH
60
VDD = 18 V
2200 pF 1000 pF
50
ISUPPLY (mA)
50
ISUPPLY (mA)
40 30
500 kHz 0
40 30 20
100 p pF
20 10 0 100
200 kHz 20 kHz
10 0 10
1000 CLOAD (pF)
10,000
100 1000 FREQUENCY (kHz)
10,000
FIGURE 2-13: Capacitive Load.
Supply Current vs.
FIGURE 2-16: Frequency.
Supply Current vs.
60
VDD = 12 V
60 2 MHz 50
ISUPPLY (mA) VDD = 12 V
2200 pF
50
ISUPPLY (mA)
40 30 20 10 0 100 1 MHz
40 30 20 10 0
100 pF 1000 p pF
500 kHz 200 kHz 20 kHz 1000 CLOAD (pF) 10,000
10
100 FREQUENCY (kHz)
1000
10,000
FIGURE 2-14: Capacitive Load.
Supply Current vs.
FIGURE 2-17: Frequency.
Supply Current vs.
60
VDD = 6 V
60
VDD = 6 V
50
ISUPPLY (mA)
50
ISUPPLY (mA)
40 30 20 10 0 100
1 MHz 500 kHz 200 kHz 20 kHz 2 MHz
40 30 20 10
100 pF 2200 pF
1000 pF
1000 CLOAD (pF)
10,000
0
10
100 1000 FREQUENCY (kHz)
10,000
FIGURE 2-15: Capacitive Load.
Supply Current vs.
FIGURE 2-18: Frequency.
Supply Current vs.
2002 Microchip Technology Inc.
DS21425B-page 7
TC4467/TC4468/TC4469
3.0 PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 3-1.
TABLE 3-1:
14-Pin PDIP, CERDIP Symbol 1A 1B 2A 2B 3A 3B GND -- 4A 4B 4Y 3Y 2Y 1Y VDD --
PIN FUNCTION TABLE
16-Pin SOIC (Wide) Symbol 1A 1B 2A 2B 3A 3B GND GND 4A 4B 4Y 3Y 2Y 1Y VDD VDD Input A for Driver 1, TTL/CMOS Compatible Input Input B for Driver 1, TTL/CMOS Compatible Input Input A for Driver 2, TTL/CMOS Compatible Input Input B for Driver 2, TTL/CMOS Compatible Input Input A for Driver 3, TTL/CMOS Compatible Input Input B for Driver 3, TTL/CMOS Compatible Input Ground Ground Input A for Driver 4, TTL/CMOS Compatible Input Input B for Driver 4, TTL/CMOS Compatible Input Output for Driver 4, CMOS Push-Pull Output Output for Driver 3, CMOS Push-Pull Output Output for Driver 2, CMOS Push-Pull Output Output for Driver 1, CMOS Push-Pull Output Supply Input, 4.5 V to 18 V Supply Input, 4.5 V to 18 V Description
DS21425B-page 8
2002 Microchip Technology Inc.
TC4467/TC4468/TC4469
4.0
4.1
DETAILED DESCRIPTION
Supply Bypassing
4.4
Power Dissipation
Large currents are required to charge and discharge large capacitive loads quickly. For example, charging a 1000 pF load to 18 V in 25 nsec requires 0.72 A from the device's power supply. To ensure low supply impedance over a wide frequency range, a 1 F film capacitor in parallel with one or two low-inductance, 0.1 F ceramic disk capacitors with short lead lengths (<0.5 in.) normally provide adequate bypassing.
The supply current versus frequency and supply current versus capacitive load characteristic curves will aid in determining power dissipation calculations. Microchip Technology's CMOS drivers have greatly reduced quiescent DC power consumption. Input signal duty cycle, power supply voltage and load type influence package power dissipation. Given power dissipation and package thermal resistance, the maximum ambient operating temperature is easily calculated. The 14-pin plastic package junction-toambient thermal resistance is 83.3C/W. At +70C, the package is rated at 800 mW maximum dissipation. Maximum allowable chip temperature is +150C. Three components make up total package power dissipation: 1. 2. 3. Load-caused dissipation (PL). Quiescent power (PQ). Transition power (PT).
4.2
Grounding
The TC4467 and TC4469 contain inverting drivers. Potential drops developed in common ground impedances from input to output will appear as negative feedback and degrade switching speed characteristics. Instead, individual ground returns for input and output circuits, or a ground plane, should be used.
4.3
Input Stage
A capacitive-load-caused dissipation (driving MOSFET gates), is a direct function of frequency, capacitive load and supply voltage. The power dissipation is:
The input voltage level changes the no-load or quiescent supply current. The N-channel MOSFET input stage transistor drives a 2.5 mA current source load. With logic "0" outputs, maximum quiescent supply current is 4 mA. Logic "1" output level signals reduce quiescent current to 1.4 mA, maximum. Unused driver inputs must be connected to V DD or VSS. Minimum power dissipation occurs for logic "1" outputs. The drivers are designed with 50 mV of hysteresis, which provides clean transitions and minimizes output stage current spiking when changing states. Input voltage thresholds are approximately 1.5 V, making any voltage greater than 1.5 V, up to VDD, a logic "1" input. Input current is less than 1 A over this range.
EQUATION
P L = fCV S f = Switching Frequency C = Capacitive Load V S = Supply Voltage A resistive-load-caused dissipation for groundreferenced loads is a function of duty cycle, load current and load voltage. The power dissipation is:
2
EQUATION
P L = D ( V S - V L )I L D = Duty Cycle V S = Supply Voltage V L = Load Voltage I L = Load Current
2002 Microchip Technology Inc.
DS21425B-page 9
TC4467/TC4468/TC4469
A resistive-load-caused dissipation for supplyreferenced loads is a function of duty cycle, load current and output voltage. The power dissipation is
EQUATION
P T = fV s ( 10 x 10 ) C = 1000 pF Capacitive Load V S = 15 V D = 50% f = 200 kHz PD = = = = Package Power Dissipation PL + PQ + PT 45mW + 35mW + 30mW 110mW
-9
EQUATION
P L = DV O I L D = Duty Cycle V O = Device Output Voltage I L = Load Current Quiescent power dissipation depends on input signal duty cycle. Logic HIGH outputs result in a lower power dissipation mode, with only 0.6 mA total current drain (all devices driven). Logic LOW outputs raise the current to 4 mA maximum. The quiescent power dissipation is:
Package power dissipation is the sum of load, quiescent and transition power dissipations. An example shows the relative magnitude for each term: Maximum operating temperature is:
EQUATION
P Q = V S ( D ( IH ) + ( 1 - D )I L ) I H = Quiescent Current with all outputs LOW (4 mA max.) I L = Quiescent Current with all outputs HIGH (0.6 mA max.) D = Duty Cycle V S = Supply Voltage Transition power dissipation arises in the complimentary configuration (TC446X) because the output stage N-channel and P-channel MOS transistors are ON simultaneously for a very short period when the output changes. The transition power dissipation is approximately: VDD 1 F Film 14 1A 1B 2A 2B 3A 3B 4A 4B 1 2 3 4 5 6 8 9 7 13 12 11 10 VOUT 470 pF +5 V Input (A, B) 0V VDD Output 0V 0.1 F Ceramic
EQUATION
T J - JA ( P D ) = 141C T J = Maximum allowable junction temperature (+150C ) JA = Junction-to-ambient thernal resistance (83.3C/W) 14-pin plastic package Note: Ambient operating temperature should not exceed +85C for "EJD" device or +125C for "MJD" device.
Input: 100 kHz, square wave, tRISE = tFALL 10 nsec 90%
10%
tD1
90% tR 10%
tD2
90% tF 10%
FIGURE 4-1:
Switching Time Test Circuit.
DS21425B-page 10
2002 Microchip Technology Inc.
TC4467/TC4468/TC4469
5.0 APPLICATIONS INFORMATION
+12 V 14
TC4469
1 2 3 A B 4 5 6 8 9 7 13 Red
Airpax #M82102-P2 7.5/Step Motor
12 Gray 11 Yel
10 Blk
FIGURE 5-1:
Stepper Motor Drive.
+5 V to +15 V 14 1 2 3 4 5 6 8 9 7
18 V
TC4469
13 12 11 10
Direction Fwd Rev
PWM Speed
M
Motor
FIGURE 5-2:
Quad Driver For H-bridge Motor Control.
2002 Microchip Technology Inc.
DS21425B-page 11
TC4467/TC4468/TC4469
6.0
6.1
PACKAGING INFORMATION
Package Marking Information
14-Lead PDIP (300 mil) Example:
XXXXXXXXXXXXXX XXXXXXXXXXXXXX YYWWNNN
TC4467CPD YYWWNNN
14-Lead CERDIP (300 mil) XXXXXXXXXXXXXX XXXXXXXXXXXXXX YYWWNNN
Example: TC4468EJD YYWWNNN
16-Lead SOIC (300 mil)
Example:
XXXXXXXXXXX XXXXXXXXXXX XXXXXXXXXXX YYWWNNN
TC4469COE YYWWNNN
Legend: XX...X YY WW NNN Note:
Customer specific information* Year code (last 2 digits of calendar year) Week code (week of January 1 is week `01') Alphanumeric traceability code
In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line thus limiting the number of available characters for customer specific information.
*
Standard OTP marking consists of Microchip part number, year code, week code, facility code, mask rev#, and assembly code.
DS21425B-page 12
2002 Microchip Technology Inc.
TC4467/TC4468/TC4469
14-Lead Plastic Dual In-line (P) - 300 mil (PDIP)
E1
D
2 n 1
E A A2
c eB A1 B1 B p
L
Number of Pins Pitch Top to Seating Plane A .140 .170 Molded Package Thickness A2 .115 .145 Base to Seating Plane A1 .015 Shoulder to Shoulder Width E .300 .313 .325 Molded Package Width E1 .240 .250 .260 Overall Length D .740 .750 .760 Tip to Seating Plane L .125 .130 .135 c Lead Thickness .008 .012 .015 Upper Lead Width B1 .045 .058 .070 Lower Lead Width B .014 .018 .022 Overall Row Spacing eB .310 .370 .430 Mold Draft Angle Top 5 10 15 Mold Draft Angle Bottom 5 10 15 * Controlling Parameter Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. JEDEC Equivalent: MS-001 Drawing No. C04-005
Units Dimension Limits n p
MIN
INCHES* NOM 14 .100 .155 .130
MAX
MIN
MILLIMETERS NOM 14 2.54 3.56 3.94 2.92 3.30 0.38 7.62 7.94 6.10 6.35 18.80 19.05 3.18 3.30 0.20 0.29 1.14 1.46 0.36 0.46 7.87 9.40 5 10 5 10
MAX
4.32 3.68 8.26 6.60 19.30 3.43 0.38 1.78 0.56 10.92 15 15
2002 Microchip Technology Inc.
DS21425B-page 13
TC4467/TC4468/TC4469
14-Lead Ceramic Dual In-line - 300 mil (CERDIP)
14-Pin CERDIP (Narrow)
PIN 1
.300 (7.62) .230 (5.84)
.098 (2.49) MAX.
.030 (0.76) MIN.
.780 (19.81) .740 (18.80) .200 (5.08) .160 (4.06) .200 (5.08) .125 (3.18) .040 (1.02) .020 (0.51) .015 (0.38) .150 (3.81) .008 (0.20) MIN.
.320 (8.13) .290 (7.37)
3 MIN.
.110 (2.79) .090 (2.29)
.065 (1.65) .045 (1.14)
.020 (0.51) .016 (0.41)
.400 (10.16) .320 (8.13) Dimensions: inches (mm)
DS21425B-page 14
2002 Microchip Technology Inc.
TC4467/TC4468/TC4469
16-Lead Plastic Small Outline (SO) - Wide, 300 mil (SOIC)
E p E1
D
2 n B h 1
45
c A A2
Units Dimension Limits n p A A2 A1 E E1 D h L c B
L A1 INCHES* NOM 16 .050 .099 .091 .008 .407 .295 .406 .020 .033 4 .011 .017 12 12 MILLIMETERS NOM 16 1.27 2.36 2.50 2.24 2.31 0.10 0.20 10.01 10.34 7.39 7.49 10.10 10.30 0.25 0.50 0.41 0.84 0 4 0.23 0.28 0.36 0.42 0 12 0 12
MIN
MAX
MIN
MAX
Number of Pins Pitch Overall Height Molded Package Thickness Standoff Overall Width Molded Package Width Overall Length Chamfer Distance Foot Length Foot Angle Lead Thickness Lead Width Mold Draft Angle Top Mold Draft Angle Bottom * Controlling Parameter Significant Characteristic
.093 .088 .004 .394 .291 .398 .010 .016 0 .009 .014 0 0
.104 .094 .012 .420 .299 .413 .029 .050 8 .013 .020 15 15
2.64 2.39 0.30 10.67 7.59 10.49 0.74 1.27 8 0.33 0.51 15 15
Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. JEDEC Equivalent: MS-013 Drawing No. C04-102
2002 Microchip Technology Inc.
DS21425B-page 15
TC4467/TC4468/TC4469
NOTES:
DS21425B-page 16
2002 Microchip Technology Inc.
TC4467/TC4468/TC4469
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013001
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2002 Microchip Technology Inc.
DS21425B-page17
TC4467/TC4468/TC4469
READER RESPONSE
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Device: TC4467/TC4468/TC4469 Questions:
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5. What deletions from the data sheet could be made without affecting the overall usefulness?
6. Is there any incorrect or misleading information (what and where)?
7. How would you improve this document?
8. How would you improve our software, systems, and silicon products?
DS21425B-page18
2002 Microchip Technology Inc.
TC4467/TC4468/TC4469
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. Device X Temperature Range
TC4467: TC4468: TC4469: C E M = = = = = = =
XX Package
Examples:
a) b) c) TC4467COE: Commerical Temperature, SOIC package. TC4467CPD: Commercial Temperature, PDIP package. TC4467MJD: Military Temperature, Ceramic DIP package. TC4468COE713: Tape and Reel, Commerical Temp., SOIC package. TC4468CPD: Commercial Temperature, PDIP package. TC4469COE: Commercial Temperature, SOIC package. TC4469CPD: Commercial Temperature, PDIP package.
Device:
1.2A Quad MOSFET Driver, NAND 1.2A Quad MOSFET Driver, AND 1.2A Quad MOSFET Driver, AND/INV 0C to +70C -40C to +85C (CERDIP only) -55C to +125C (CERDIP only) Plastic DIP, (300 mil body), 14-lead Ceramic DIP, (300 mil body), 14-lead SOIC (Wide), 16-lead SOIC (Wide), 16-lead (Tape and Reel)
a) b)
Temperature Range:
a) b)
Package:
PD JD OE OE713
Sales and Support
Data Sheets Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following: 1. 2. 3. Your local Microchip sales office The Microchip Corporate Literature Center U.S. FAX: (480) 792-7277 The Microchip Worldwide Site (www.microchip.com)
Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using. New Customer Notification System Register on our web site (www.microchip.com/cn) to receive the most current information on our products.
2002 Microchip Technology Inc.
DS21425B-page19
TC4467/TC4468/TC4469
NOTES:
DS21425B-page 20
2002 Microchip Technology Inc.
TC4467/TC4468/TC4469
Information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. No representation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip's products as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights.
Trademarks The Microchip name and logo, the Microchip logo, FilterLab, KEELOQ, microID, MPLAB, MXDEV, PIC, PICmicro, PICMASTER, PICSTART, PRO MATE, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. dsPIC, dsPICDEM.net, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, microPort, Migratable Memory, MPASM, MPLIB, MPLINK, MPSIM, MXLAB, PICC, PICDEM, PICDEM.net, rfPIC, Select Mode and Total Endurance are trademarks of Microchip Technology Incorporated in the U.S.A. Serialized Quick Turn Programming (SQTP) is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. (c) 2002, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved.
Printed on recycled paper.
Microchip received QS-9000 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona in July 1999 and Mountain View, California in March 2002. The Company's quality system processes and procedures are QS-9000 compliant for its PICmicro(R) 8-bit MCUs, KEELOQ(R) code hopping devices, Serial EEPROMs, microperipherals, non-volatile memory and analog products. In addition, Microchip's quality system for the design and manufacture of development systems is ISO 9001 certified.
2002 Microchip Technology Inc.
DS21425B-page 21
M
WORLDWIDE SALES AND SERVICE
AMERICAS
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EUROPE
Denmark
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India
Microchip Technology Inc. India Liaison Office Divyasree Chambers 1 Floor, Wing A (A3/A4) No. 11, O'Shaugnessey Road Bangalore, 560 025, India Tel: 91-80-2290061 Fax: 91-80-2290062
United Kingdom
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Austria
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05/16/02
DS21425B-page 22
2002 Microchip Technology Inc.


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